1. Field of the Invention
Generally, the present disclosure relates to the field of manufacturing of integrated circuits and semiconductor devices, and, more particularly, to electrically programmable fuses, for example, in SOI configurations.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of electronic circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for many types of complex circuitry, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. Miniaturization and increase of circuit densities represent ongoing demands.
In order to improve the product yield, a technique has been developed of “trimming” or electrically excluding circuit blocks which are no longer operable. This technique, particularly used during manufacturing of memory arrays, relies on redundant circuit blocks which can be incorporated into the main integrated circuit and activated once a defective circuit portion has been detected. On the other hand, the defective circuit block may be trimmed or electrically removed by blowing a fuse or a group of fuses which can electrically disconnect the defective block from the main circuit when in the open configuration. Reprogramming of an integrated circuit is thus rendered possible in a dynamic manner, even after the chip has been manufactured.
Electronic fuses (e-fuses; the terms “fuse” and “e-fuse” are used as interchangeable terms herein) may be used in complex integrated circuits as important mechanisms to allow adapting the performance of certain circuit portions to comply with performance of other circuit portions, for instance after completing the manufacturing process and/or during use of the semiconductor device, for instance when certain critical circuit portions may no longer comply with corresponding performance criteria, thereby requiring an adaptation of certain circuit portions, such as re-adjusting an internal voltage supply, thereby re-adjusting overall circuit speed and the like.
Electronic fuses provided in the semiconductor devices represent electronic switches that may be activated once in order to provide a desired circuit adaptation. Hence, the electronic fuses may be considered as having a high impedance state, which typically represents a programmed state, and having a low impedance state, typically representing a non-programmed state of the electronic fuse. Since these electronic fuses may have a significant influence on the overall behavior of the entire integrated circuit, a reliable detection of the non-programmed and the programmed state has to be guaranteed, which is accomplished on the basis of appropriately designed logic circuitry. Furthermore, since typically these electronic fuses may be actuated only once over the lifetime of the semiconductor device under consideration, a corresponding programming activity has to ensure that a desired programmed state of the electronic fuse is reliably generated in order to provide well-defined conditions for the further operational lifetime of the device.
The programming of an e-fuse typically involves the application of a voltage pulse, which in turn induces a current pulse of sufficient current density in order to cause a permanent modification of a specific portion of the fuse. Thus, the electronic behavior of the fuse and the corresponding conductors for supplying the current and voltage to the fuse have to be precisely defined to obtain a reliable programmed state of the fuse. For this purpose, polysilicon is conventionally used for the fuse bodies, for instance in combination with a metal silicide, in which electromigration effects, in combination with other effects, caused by the current pulse, such as a significant heat generation, may then result in a permanent line degradation, thereby generating a high-Ohmic state of the fuse body.
The cross-section of a conventionally formed e-fuse 100 is shown in FIG. 1. The e-fuse 100 is formed on an isolation region 112 formed in a substrate (not shown). The substrate may be any appropriate carrier for a semiconductor integrated device. The isolation region 112 may, for example, have been formed by means of shallow trench isolation (STI). The e-fuse 100 includes a metal layer 124 formed above the surface of the isolation region 112. The material or material mixture constituting the layer 124 is typically the same as a material or material mixture used for a gate metal layer in devices fabricated using high-k/metal-gate (HKMG) technology. Although not shown in FIG. 1, a high-k dielectric layer may be interposed between the metal layer 124 and the surface of the isolation region 112.
A semiconductor layer 144 is then formed on the metal layer 124. The semiconductor layer 144 is preferably the same material used for forming the gate material layer on the gate metal layer. Thus, the semiconductor layer 144 is usually comprised of polysilicon. A metal silicide layer 164, typically nickel silicide, is finally formed on the surface of the semiconductor layer 144. The metal silicide layer 164 is conveniently formed during the same silicidation process used for forming electrical contacts to the electrodes (gate, source and drain) of a FET. The metal silicide layer 164 includes a first electrode 164a and a second electrode 164c arranged at opposite ends of the layer 164. The first electrode 164a and the second electrode 164c could, for example, be the anode and the cathode of the e-fuse 100. Contact terminals 174a and 174b are then formed so as to provide an electrical connection to the first electrode 164a and the second electrode 164c, respectively. The contact terminals 174a and 174b are typically comprised of a metal with a high electrical conductivity. When the e-fuse 100 is un-programmed, the metal silicide layer 164 is continuous and provides an electrical connection between the first electrode 164a and the second electrode 164c, thus presenting a low electrical resistance between terminals 174a and 174b. 
The e-fuse 100 may then be programmed by applying a predetermined electrical bias between terminals 174a and 174b, thereby inducing a current to flow across the e-fuse 100. Since the resistivity of the semiconductor layer 144 is much greater than that of the silicide layer 164, almost all current flows through the silicide layer 164. If the current intensity exceeds a predetermined threshold, electromigration occurs in the silicide layer 164, resulting in transport of the metal silicide material constituting the layer 164 towards the anode. After a sufficient amount of material has been transferred to one of the two electrodes 164a and 164c representing the anode, the e-fuse 100 switches to the programmed state when a gap (not shown) is formed in the metal silicide layer 164, thereby resulting in an open circuit between the two terminals 174a and 174b. The electrical resistance of the programmed e-fuse 100 thus rises by several orders of magnitude with respect to the resistance in the un-programmed state.
However, in the course of aggressive downscaling, for example, in the context of sub 28 nm or even sub 22 nm Very Large Scale Integrated (VLSI) Circuits CMOS technologies, the conventional manufacture of e-fuses as the one shown in FIG. 1 proves to be very complicated and bears the risk of severe failures, for example, caused by insufficient electrical isolation between the HKMG and the silicided layer. Moreover, conventionally formed e-fuses have a demand for relatively large areas and e-fuses realized in back end-of-line (BEoL) stacks typically suffer from the need for relatively high currents for blowing the fuses. Fuses located in silicon layers of non-SOI device portions of a semiconductor substrate show bad thermal isolation due to the relatively high thermal conductivity of silicon.
In view of the situation described above, the present disclosure provides a new kind of e-fuse and techniques for the formation of the same that overcome the above-mentioned problems and provide for reliable operation at relatively low programming currents and with good thermal isolation.